Josep Torrellas is a Professor at the Departments of Computer Science and (by courtesy) Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He is the Director of the Center for Programmable Extreme-Scale Computing, and past Director of the Illinois-Intel Parallelism Center. His research interests are shared-memory parallel computer architecture, low-power architectures, hardware reliability, and software dependability. He has published over 200 publications in top conferences and journals, and received 12 Paper Awards. His recent research projects as part of the Intel Center include the Bulk Multicore architecture designed for parallel programming productivity, and the x86-compatible QuickRec hardware prototype for record and replay of parallel programs. He is also involved in designing the Intel-lead Runnemede Extreme-Scale Manycore funded by DARPA’s UHPC program, and in developing a variation-aware low-voltage processor under DARPA’s PERFECT program. His past projects include the IBM PERCS multiprocessor funded under DARPA’s HPCS program, the FlexRAM Intelligent Memory architecture funded by NSF, and the I-Acoma Multiprocessor, which was one of the Ten Design Point Studies that were pushed nationwide to attain a petaflop machine. Torrellas’ group has also developed widely-used software, such as the SESC architecture simulator and the VARIUS models of process variation.
Torrellas is a Fellow of IEEE (2004) and ACM (2010). He has been a Willett Faculty Scholar at Illinois. He has served as the Chair of the IEEE Computer Society Technical Committee on Computer Architecture (TCCA) from 2005 to 2010, and as a Council Member of CRA’s Computing Community Consortium (CCC) from 2011 to 2014. He has contributed to several research visioning workshops that have resulted in funding solicitations. He has graduated 35 Ph.D. students, who are now leaders in the field, including 12 who are faculty in top US universities. Torrellas received a PhD from Stanford University in 1992.
2015 Technical Achievement Award
“For pioneering contributions to shared-memory multiprocessor architectures and thread-level speculation.”
Learn more about the Technical Achievement Award