According to Moore’s law, the scaling of microelectronic technology allows for increasing system performance and complexity, thus paving the way for innovative applications that were unthinkable just a few years earlier. However, that same shrinking feature size increases the vulnerability of integrated circuits (ICs) to aging phenomena such as bias temperature instability (BTI), which pose new challenges for IC reliability.
The September Computing Now theme examines these challenges, as well as some approaches to solving them.
Aging ICs in a New Era
The miniaturization of electronic features increases the likelihood of physical defects and parametric variations during fabrication, thus posing new challenges for testing and reliability. Traditional test techniques, such as burn-in, are becoming less effective owing to power and voltage constraints and might soon become infeasible. Burn-in has limited effectiveness in activating faults that are likely to occur in the first years of circuit operation in the field. This, along with the scaling of transistors’ gate insulators, is making aging phenomena more likely to affect the circuit in the field, potentially compromising its operation and increasing reliability risks.
Interface-state generation and charge trapping both cause BTI. BTI produces a significant threshold-voltage shift in metal-oxide-semiconductor field-effect (MOSFET) transistors, both those using hafnium-based high-k dielectric material and those using pure silicon dioxide (SiO2). Negative and positive BTI (NBTI and PBTI) are observed in N-type and P-type MOS (NMOS and PMOS) transistors, respectively.
When transistors are biased in strong inversion (stress phase), that is when their channel is formed, the BTI caused threshold voltage shift considerably degrades transistors’ performance, thus resulting in delayed signals’ transitions. Such degradation in the datapaths of high-performance systems can make the signals feeding flip-flops violate their setup and hold times. This can result in incorrect data sampling and output errors. The BTI-induced performance degradation is partially offset when the transistors are turned off (the recovery phase).
While accurately modelling BTI degradation has been addressed since several years, analyzing its impact on the in-field operation of electronic circuits and devising approaches to avoid their consequent incorrect operation has become of major concern only recently, due to the continuous scaling of microelectronic technology and the limited effectiveness of burn-in.
This month’s theme articles provide a solid reference for IC-aging analysis, monitoring, and compensation — both at the end of fabrication and in the field.
We open with “Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops,” in which Usman Khalid and his colleagues analyze the joint effect of process variations and NBTI on the noise margins of different kinds of flip-flops. They performed their evaluation by means of transistor-level Monte Carlo simulations, producing both nominal values and associated standard deviations of the noise margins of the selected flip-flops. Their results show that, as for noise margins’ robustness to joint aging and variability effects, pseudo-static and dynamic flip-flops outperform those that are fully static.
Next up, Xiaofei Wang and his colleagues propose a solution to the problem of BTI measuring. “Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design” presents innovative on-chip aging monitors, dubbed silicon “odometers.” They consist of ring oscillators, some of which serve as reference and others are to be stressed at the end of fabrication. The authors derive an estimation of BTI by comparing the frequency of the signals generated by the stressed ring oscillators against those generated by the reference oscillators. The designs were implemented in six test chip projects using process technologies ranging from 32 to 130 nm.
Finally, in “Low Cost NBTI Degradation Detection and Masking Approaches,” Martin Omaña and his colleagues address the problem of monitoring NBTI in the field and keeping it from compromising system operation. They propose two monitoring-and-masking approaches to detect late signal transitions in the field due to NBTI degradation in the combinational part of critical datapaths. They prevent those identified transitions from causing incorrect data by sampling the flip-flops at the end of the datapaths, thus guaranteeing output data correctness. In the low area and power (LAP) approach, a monitoring circuit provides an alarm message when NBTI causes the late transitions. That message activates a clock-frequency adaptation phase, avoiding the generation of incorrect data. The LAP approach features lower area overhead and lower (or comparable) power consumption than previous approaches, while offering the same impact on performance. In the high-performance (HP) approach, a monitoring circuit overwrites the incorrect data produced at the outputs of the monitored flip-flops. The HP approach reduces the impact on system performance compared to previous alternatives, but with some increase in area and power consumption.
For interested readers, some additional articles that explore deeper aspects of the challenges posed by aging ICs are available in the IEEE Xplore digital library (requires login). A good place to start is “Impact of Bias Temperature Instability on Soft Error Susceptibility”, which I coauthored with Daniele Rossi, Martin Omaña, and Alessandro Paccagnella. After discussing the physical phenomena contributing to BTI degradation, we analyze how BTI affects the vulnerability of combinational circuits to radiation-induced errors (soft errors) in the field. BTI increases ICs’ vulnerability, with a maximal impact in the first two to three years of IC lifetime. This contrasts with more traditional soft-error vulnerability models, which ignore IC lifetime and aging. We propose a dynamic model to estimate IC vulnerability to soft errors with circuit aging, which is accurate with respect to electrical-level simulations. Such a model could enable adaptive solutions to counteract the detrimental effect of BTI on IC vulnerability to soft errors.
In “Bias Temperature Instability Analysis of FinFET based SRAM cells,” Seyab Khan and his colleagues analyze BTI’s effects on memory elements, particularly MOSFET and FinFET transistor SRAM cells. They evaluate the effects of NBTI only, PBTI only, and BTI (both NBTI and PBTI) by considering two SRAM designs (a six-transistor and an eight-transistor SRAM cell) and show that FinFET-based SRAM cells are more vulnerable to BTI degradation than MOSFET-based cells.
“A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology,” by Tony Tae-Hyoung Kim and his colleagues, proposes ring-oscillator-based test structures that can separately measure NBTI and PBTI degradation effects in digital circuits using high-k metal gate transistors at the end of fabrication. Because the magnitude of NBTI and PBTI is different after a given stress time, the impact on circuit performance should be estimated independently. To estimate aging effects, the authors compare digitized results from both stressed ring oscillators and reference ring oscillators. Such digitized output data can be further exploited to control various circuit parameters to warn of system failures or compensate for degradation.
Dan Alexandrescu on aging semiconductor devices. Video transcript (pdf).
This month’s theme also includes a video in which Dan Alexandrescu from iRoC Technologies provides deep technical insight into these issues.
We hope this issue of Computing Now serves as a resource to highlight the major challenges of aging ICs and stimulates further research in the field.
C. Metra, “Are Our Electronic Circuits Getting Older?,” Computing Now, vol. 8, no. 9, September 2015, IEEE Computer Society [online]; http://www.computer.org/publications/tech-news/computing-now/are-our-electronic-circuits-getting-older.
Cecilia Metra is Computing Now’s editor in chief and a full professor of electronics at the University of Bologna. Her research interests are the design and test of digital systems, reliable and error-resilient system design, fault tolerance, online testing, fault modeling, diagnosis and debugging, emergent technologies and nanocomputing, secure systems, energy-harvesting systems, and photovoltaic systems. Metra received a PhD in electronic engineering and computer science from the University of Bologna. She is a member of the IEEE Computer Society’s Board of Governors and Executive Committee, and has been the society’s Vice President for Technical and Conference Activities. She has also been associate editor in chief of IEEE Transactions on Computers. She’s on the editorial boards of several professional journals and has served as a general chair, program chair, program cochair, or technical-program committee member for numerous IEEE-sponsored conferences, symposia, and workshops. In 2002, she was a visiting faculty consultant for Intel in the US. She’s an IEEE Fellow and a Golden Core member of the IEEE Computer Society, from which she has received three Meritorious Service Awards and two Certificates of Appreciation. Contact her at email@example.com.