September 2010 Theme:
Hardware Security and Trust
Guest Editors' Introduction by Mohammad Tehranipoor and Farinaz Koushanfar
 

Hardware security and trust issues span a broad spectrum of topics, including

  • the malicious insertion of hardware Trojans designed to act as silicon time bombs by enabling chips upon fabrication and disabling them upon tampering,
  • intellectual property (IP) and integrated circuit (IC) piracy,
  • digital rights management,
  • untrusted third-party IP cores,
  • attacks designed to extract encryption keys and IP from ICs, and
  • malicious system disruption and diversion.

This special issue includes four articles covering various aspects of hardware security and trust and provides insight and novel solutions for addressing these challenges.

In this Issue

In “A Survey of Hardware Trojan Taxonomy and Detection,” (login required for full text) we discuss vulnerabilities in today’s design and fabrication processes and the possibility of malicious circuit insertion into a design that can impact the design’s functionality or enable transmitting key information to the adversary. The hardware Trojan detection problem has gained significant attention over the past few years, and we provide a comprehensive overview and analysis of the current state of knowledge in this area.

The second article, “Hardware Trojans in Wireless Cryptographic ICs” (login required for full text) by Yier Jin and Yiogos Makris, studies the problem of hardware Trojans in wireless cryptographic ICs. Using a mixed-signal SoC, Jin and Makris demonstrate that simple malicious modifications to the digital part of a wireless cryptographic chip would suffice to leak information without changing the more sensitive analog part. They design two hardware Trojans that leak the encryption key by manipulating the transmission amplitude or frequency. The Trojans are designed so that they change neither the functionality of the digital part nor the performance of the analog part, and their impact on the wireless transmission parameters can be hidden within the fabrication process variations. The authors present an advanced statistical analysis for the transmission power to reveal a Trojan’s presence.

Hardware Trojan Horse Detection Using Gate-Level Characterization,” (login required for full text) by M. Potkonjak et al. (login required), provides an impetus for hardware Trojan research by creating a generic and easily applicable set of techniques and tools for Trojan detection. The authors introduce a technique for recovery of characteristics of gates in terms of leakage current, switching power, and delay, which uses linear programming to solve a system of equations created by non-destructive measurements of power or delays.

In the fourth article, “Design Methods for Security and Trust,” (login required for full text) I. Verbauwhede and P. Schaumont argue that security and trust are usually an afterthought during the design of ubiquitous and embedded computers. The authors outline a methodology for the design of secure and trusted electronic embedded systems, which builds on identifying the secure-sensitive part of a system and iteratively partitioning and protecting it at all levels of design abstraction.

The fifth article, “Silicon Physical Random Functions” (login required for full text) by B. Gassend et al. (login required), describes the notion of physical unclonable functions (PUF) and develops several circuit realizations of different PUFs. The authors describe the application of PUFs to design of secure smart cards, licensing, and certification.

The last article, “Preventing IC Piracy Using Reconfigurable Logic Barriers” (login required for full text) by Alex Baumgarten, Akhilesh Tyagi, and Joseph Zambreno, addresses IC piracy prevention. The approach adds reconfigurable logic barriers to the IC pre-fabrication. These barriers separate the inputs from the outputs such that every path from inputs to outputs passes through a barrier. The IC would function correctly only when the correct keys are applied to the barriers. The barrier insertion heuristic utilizes the don’t-care sets and the node locations in the network to maximize the reverse-engineering effort while limiting the overhead.

We sincerely hope that you will enjoy reading this special issue, and we would like to thank all the authors for their tremendous efforts in producing these high-quality articles.


Guest Editors

Mohammad Tehranipoor is an associate professor of electrical and computer engineering at the University of Connecticut, Storrs. Contact him at http://www.engr.uconn.edu/~tehrani or tehrani@engr.uconn.edu.

Farinaz Koushanfar is an assistant professor of electrical and computer engineering and the director of Texas Instruments DSP Leadership at Rice University. Contact her at http://www.ece.rice.edu/~fk1 or farinaz@rice.edu.


Related Multimedia

Listen to the Guest Editors introduce the theme.

Download Mohammad Tehranipoor’s video introduction (.flv)

Download Farinaz Koushanfar’s video introduction (.flv)